Today, parallelism and multi-core processors are a mainstream technology for a magnitude of computer systems, from small embedded systems to large-scale server systems. As a result, the software must also be adapted to this new type of target platform. One of the largest challenges when developing software for multi-core processors is to identify and introduce enough parallelism in the applications in order to utilize the performance potential of multi-core processors. Another approach to exploit parallelism is based on reconfigurable hardware accelerators. This makes it possible to efficiently implement signal and image processing applications that exhibit data parallelism, and do so with high performance and in an energy-efficient way. Programming such devices is however difficult and need to be atomized.
In Theme B we work on development as well as execution environments for multi-core processors and reconfigurable hardware accelerators. Theme B consists of two different parts, each exploiting one of the approaches describe above. The research includes methods, techniques, and tools for parallelization, programmer support, and correctness as well as performance analysis. We primarily work on code and applications that execute within a mobile terminal (’intra-device’).
The second part concentrates on programming and compilation for weakly programmable processor arrays, i.e., reconfigurable computer architectures composed of many small programmable processors with local memory. The processors have high-performance local communication but lack a shared memory. This provides a flexible execution platform for implementing computation intensive applications in an energy efficient way using parallel execution for delivering good performance. The challenge is to map applications, which usually assume a global state, to an architecture with local state. We are working on tools and compilers to aid the programmer with this task.